1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a synchronous dynamic random access memory (SDRAM) device which operates in synchronism with an external clock signal. More specifically, the present invention is concerned with a precharge protection of the SDRAM device.
2. Description of the Related Art
Various types of semiconductor memory devices such as a DRAM device and an SDRAM device have been proposed. The semiconductor memory devices of different types are selectively used in terms of applications thereof. Recently, applications and systems have required DRAM devices having a large storage capacity. In the above situation, the SDRAM device is attractive which can operate in synchronism with an external clock signal having a very high speed.
The SDRAM device requires a refresh operation as in the case of the general DRAM devices. The recent DRAM devices have a plurality of refresh modes such as an auto refresh mode and a self refresh mode. The auto refresh mode requires an external clock and an external address, while the self refresh mode does not require them. The self refresh mode can hold data at the time of a system standby without external signals. More particularly, the self refresh mode activates a circuit which sequentially generates a row address, and a circuit which drives a row (word line) corresponding to the row address, and repeatedly performs a precharge operation. The auto refresh mode activates the circuit which sequentially generates the row address and the circuit which drives the row (word line) corresponding to the row address, and performs the precharge operation only one time.
The refresh mode in the general DRAM device is selected by controlling predetermined signals such as a column address strobe signal /CAS and a row address strobe signal /RAS at given timings. The above is called by command entry. For example, a CAS-before-RAS command makes entry of the auto refresh mode. After the cycle of the above entry, entry of the self refresh mode can be made by holding the column address strobe signal /CAS for a predetermined time (equal to, for example, 100 .mu.m). The symbol "/" denotes an active-low signal.
In the SDRAM device, the auto refresh mode and the self refresh mode can be made by controlling a clock enable signal CKE which indicates whether the SDRAM device should receive a synchronous clock signal CLK, a chip select signal /CS, /RAS, /CAS and a write enable signal /WE. For example, entry of the auto refresh mode can be made when the clock enable signal CKE is successively high during two cycles in a state in which the signals /CS, /RAS, /CAS are each low (L) and the signal /WE is high (H). Entry of the self refresh mode can be made if the signals /CS, /RAS and /CAS are low and the write enable signal /WE is high at the time when the clock enable signal CKE switches from H to L. An external control of the SDRAM device can be interrupted at any time by applying a command synchronized with the clock signal thereto. The commands can be interpreted by a command decoder provided in the SDRAM device.
The normal read and write operations of the SDRAM devices can be carried out by applying corresponding commands thereto. In these operations, modes are set by applying commands in the order of an active mode and a precharge mode. In the active mode, the external address is received and recognized as a row address. Next, a circuit which selects a row select line corresponding to the recognized row address is activated. Then, a circuit which activates a sense amplifier corresponding to a column address to output data to a data bus is activated. In the precharge mode, only an address part which is contained in the row address and is related to a bank control is accepted and the precharge operation in the chip is initiated.
However, the above-mentioned DRAM and SDRAM devices have the following disadvantages.
Generally, in the DRAM and SDRAM devices, the self refresh command and the auto refresh command are inhibited from being applied thereto while an internal circuit is operating. This is an illegal state. However, in practice, the DRAM and SDRAM devices may be switched to a command acceptable state due to noise or an influence of an element in a peripheral circuit. If such a state happens, the refresh operation is carried out by the above command before the operation of a mode in an internal circuit is completed. This may destroy data. In other words, the self refresh mode or auto refresh mode is started before the precharge operation in each mode. Hence, it is necessary to define a certain period which ensure completion of the precharge operation and inhibits acceptance of any commands.
The conventional DRAM and SDRAM devices is equipped with a protection circuit which defines the above period. The protection circuit defines a precharge protection period for which the precharge operation is ensured. Generally, the precharge protection period is selected so as to be equal to the smallest one of precharge protection periods which are required in the respective modes. The smallest, namely, minimum precharge period is related to the data read or write operation. As has been described previously, the active mode and the precharge mode are set in this sequence in order to perform the data read/write operation. For the next data read or write, the active mode is set after the setting of the precharge mode, and then the precharge mode is set. That is, the setting of the active mode and the precharge mode is repeatedly carried out. The above protection period is determined based on the time of the precharge mode. The completion of the active mode is released by the setting of the precharge mode, which is set in the device.
The protection period thus determined is too short to protect the precharge in the self refresh mode and the auto refresh mode. In the self refresh mode and the auto refresh mode, the refresh operation is completed by a single command, and is different from the operations which are stopped by the next command. In the self refresh mode and the auto refresh mode, the sense operation of the sense amplifier is carried out as in the case of the normal read and write operations. A necessary and sufficient period is defined for the sense operation, and the precharge operation is automatically initiated immediately after the above period. The necessary and sufficient period for the sense operation is different from the period at the end of which period the sense operation in the active mode for the normal data read or write operation is terminated by a command input to the precharge mode, and is longer than the above period. Hence, if the sum of the period of the sense operation and that of the precharge operation is constant, a longer protection time can be defined for the self refresh mode and the auto refresh mode. However, in practice, the protection period is determined in common to each mode including the self refresh mode and the auto refresh mode. Since the protection period thus determined is too short to protect the precharge in the self refresh mode and the auto refresh mode, an error may occur in these modes due to noise or an influence of an element in the peripheral circuit. However, if an appropriate (longer) precharge protection period is defined for the auto refresh and self refresh modes, occurrence of such an error will be prevented.